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MPLAB^® XC32 Compiler

MPLAB® XC32 Compiler

The MPLAB^® XC32 C/C++ Compiler is a powerful, optimizing compiler that converts your ISO C and C++ programs into high-performance, assembly-language instructions to run bare metal on our 32-bit PIC^® microcontrollers and SAM microcontrollers and microprocessors. This compiler offers many command-line options and language extensions that enable full access to the device’s hardware features, including Tightly Coupled Memory (TCM), L1 cache coherence, and best-fit memory allocation.

Whether you're working on Microchip devices with 32-bit Arm^®or MIPS^® cores, the MPLAB XC32 Compiler empowers you to optimize and fine-tune your code for efficiency and minimize your development time for bare-metal or RTOS embedded applications.

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Compiler Optimizations

Get advanced optimization capabilities, including reduced code size and faster execution, without licensing friction or budget constraints. All MPLAB XC Compiler optimizations are now available at no cost.

MPLAB XC32 Compiler v6.00 and later do not require a key to access advanced optimizations. To unlock the premium capabilities of previously paid versions, there is a free license in the software products section of your myMicrochip account.

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MPLAB XC32 C/C++ Compiler v6.00 Released

Upgrade to MPLAB XC32 version 6.00 to take advantage of significant performance and productivity improvements:

Removed license restrictions for optimization features: All MPLAB XC compilers, including MPLAB XC32, are now available without license restrictions, providing all users with full access to compiler optimization capabilities at no cost
Reduced code size on entry-level Arm^® Cortex-M devices: The compiler automatically eliminate redundancies, generate compact compare-and-branch encodings and improve register allocation on Cortex-M targets. These enhancements reduce flash memory usage on resource-constrained PIC32C and SAM microcontrollers without requiring source code changes.

Faster application startup on Error Correction Code (ECC) Random-Access Memory (RAM) devices: A new opt-in, word-oriented data initialization mode initializes variables and clears Block Started by Symbol (BSS) regions using aligned word stores instead of byte-by-byte copies. This approach meets ECC RAM write requirements and reduces time spent in startup code before main() is entered.

Improved reliability on ECC-protected memory targets: The compiler automatically detects and initializes unused RAM regions, including stack, heap and other clearable areas before first access. This behavior helps prevent ECC fault conditions that would otherwise require manual startup code modifications.

Simplified multi-threaded PIC32M application development with native thread-local storage: MIPS^® targets now support the standard __thread and _Thread_local storage class specifiers. This support enables each Real-Time Operating System (RTOS) thread to maintain its own instance of of global and static variables without manual synchronization , or changes to existing startup code or linker scripts.